1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise gate structures including a high-k gate dielectric material and a metal-containing electrode material provided in an early manufacturing stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of integrated circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers in the channel region.
The continuous shrinkage of critical dimensions of transistor elements has resulted in a gate length of field effect transistors of 50 nm and significantly less, thereby providing sophisticated semiconductor devices having enhanced performance and an increased packing density. The increase of electrical performance of the transistors is strongly correlated with a reduction of the channel length, which may result in an increased drive current and switching speed of the field effect transistors. On the other hand, the reduction of the channel length is associated with a plurality of issues in terms of channel controllability and static leakage currents of these transistors. It is well known that field effect transistors with a very short channel may require an increased capacitive coupling between the gate electrode structure and the channel region in order to provide the desired static and dynamic current flow controllability. Typically, the capacitive coupling is increased by reducing the thickness of the gate dielectric material, which is typically formed on the basis of a silicon dioxide base material, possibly in combination with a nitrogen species, due to the superior characteristics of a silicon/silicon dioxide interface. Upon implementing a channel length of the above-identified order of magnitude, however, the thickness of the silicon dioxide-based gate dielectric material may reach values of 1.5 nm and less, which in turn may result in significant leakage currents due to a direct tunneling of the charge carriers through the very thin gate dielectric material. Since the exponential increase of the leakage currents upon further reducing the thickness of silicon dioxide-based gate dielectric materials is not compatible with the thermal power design requirements, other mechanisms have been developed so as to further enhance transistor performance and/or reduce the overall transistor dimensions.
For example, by creating a certain strain component in the channel region of silicon-based transistor elements, the charge carrier mobility and, thus, the overall conductivity of the channel may be enhanced. For a silicon material with a standard crystallographic configuration, i.e., a (100) surface orientation with the channel length direction oriented along a <110> equivalent direction, tensile strain in the current flow direction may enhance conductivity of electrons, thereby improving transistor performance of N-channel transistors. On the other hand, generating a compressive strain in the current flow direction may increase the mobility of holes and may, thus, provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past, wherein internal strain-inducing sources, such as an embedded strain-inducing semiconductor material, have proven to be very efficient strain-inducing mechanisms. For example, frequently, the incorporation of a compressive strain-inducing silicon/germanium alloy in the drain and source areas of P-channel transistors is applied in order to enhance performance of these transistors. For this purpose, in an early manufacturing stage, cavities are formed in the active region laterally adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer and a resist mask. These cavities may be subsequently refilled with the silicon/germanium alloy on the basis of selective epitaxial growth techniques. During the etch process for forming the cavities and during the subsequent epitaxial growth process, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose sensitive materials of the gate electrode structure, such as a silicon-based electrode material, to the process ambient for forming the cavities and for selectively growing the silicon/germanium alloy. Thereafter, the gate electrode structures may be exposed and the further processing may be continued by forming drain and source regions in accordance with any appropriate process strategy.
Basically, the above-described strain-inducing mechanism is a very efficient concept for improving transistor performance of P-channel transistors, wherein the efficiency of the finally obtained strain in the channel region of the transistor, however, strongly depends on the internal strain level of the semiconductor alloy and on the lateral offset of this material from the channel region. Typically, the material composition of the strain-inducing semiconductor alloy is restricted by currently available sophisticated selective epitaxial deposition recipes, which, in the case of a silicon/germanium alloy, may presently not allow germanium concentrations of significantly more than approximately 30 atomic percent. Consequently, a further improvement of the total strain in the channel region requires a reduction of the lateral offset of the silicon/germanium alloy from the channel region so that any protective spacer structures may have to be provided with a reduced width.
In addition to providing strain-inducing mechanisms in field effect transistors, also sophisticated gate electrode materials have been proposed in order to overcome the restrictions of conventional silicon dioxide/polysilicon-based gate electrode structures. To this end, the conventional silicon dioxide-based gate dielectric material is replaced, at least partially, by a so-called high-k dielectric material, i.e., a dielectric material having a dielectric constant of 10.0 and higher, which may result in a desired high capacitance between the gate electrode and the channel region, while nevertheless a certain minimum physical thickness is provided so as to keep the resulting leakage currents at an acceptable level. For this purpose, a plurality of dielectric materials, such as hafnium oxide-based materials, zirconium oxide, aluminum oxide and the like, are available and may be used in sophisticated gate electrode structures. Furthermore, the polysilicon material may also be replaced, at least in the vicinity of the gate dielectric material, since typically polysilicon suffers from charge carrier depletion in the vicinity of the gate dielectric material, which may reduce the effective capacitance. Moreover, with sophisticated high-k gate dielectric materials, the work function of standard polysilicon materials obtained by a corresponding doping may no longer be sufficient to provide the required electronic characteristics of the gate electrode material in order to obtain a desired threshold voltage of the transistors under consideration. For this reason, specific work function adjusting metal species, such as aluminum, lanthanum and the like, are typically incorporated in the gate dielectric material and/or in an appropriate electrode material in order to obtain a desired work function and also increase conductivity of the gate electrode material at least in the vicinity of the gate dielectric material.
Thus, a plurality of sophisticated process strategies have been developed, wherein, in some promising approaches, the sophisticated gate materials, such as a high-k dielectric material and a metal-containing electrode material, possibly including a work function adjusting metal species, may be provided in an early manufacturing stage in combination with a polysilicon material, thereby providing a high degree of compatibility with conventional process strategies for forming sophisticated field effect transistors. It turns out, however, that a reliable confinement of the sensitive material system, including the high-k dielectric material and the metal-containing electrode material, has to be guaranteed in order to avoid a shift in threshold voltage or any other variabilities of the sophisticated high-k metal gate electrode structures.
In an attempt to further enhance device performance of sophisticated field effect transistors, it has been proposed to combine sophisticated high-k metal gate electrode structures with a strain-inducing mechanism, for instance, by incorporating a strain-inducing semiconductor alloy in the active regions of the transistors. In this case, the encapsulation of the gate electrode structure of the transistor may have to be implemented on the basis of detrimental requirements. On the one hand, the confinement of the gate electrode structure has to ensure integrity of the sensitive material system, for example, prior to, during and after the incorporation of the strain-inducing semiconductor material, and, on the other hand, a reduced thickness of any protective spacer elements, such as silicon nitride-based materials, is to be implemented in view of enhancing efficiency of the strain-inducing mechanism. Consequently, a compromise of the thickness of the spacer elements and gain in performance of sophisticated transistors is typically applied.
Upon further scaling the transistors elements, increasing yield loss has been observed when forming high-k metal gate electrode structures in an early manufacturing stage, which is believed to be caused by insufficient encapsulation, in particular of the sensitive gate metal materials, even if the liner width is applied that is still compatible with the overall design rules. Without restricting the present application to the following explanation, it is assumed that, in particular, the pronounced topography of isolation regions in the vicinity of active regions has a significant influence on gate failure mechanisms, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a top view of a semiconductor device 100 or the layout thereof corresponding to a manufacturing stage in which gate electrode structures are formed so as to extend above active regions and isolation regions of the device 100. In the example shown, active regions 102a, 102b, 102c, 102d are provided as required by a specific layout, wherein, for instance, the active regions 102a, 102b may correspond to P-channel transistors and N-channel transistors, respectively. Similarly, the active regions 102c, 102d may correspond to a P-channel transistor and an N-channel transistor, respectively. Furthermore, as shown, gate electrode structures 160a, 160b may represent common gate electrode structures for transistors to be formed in and above the active regions 102a, 102b, while corresponding gate electrode structures 160c, 160d may be formed above the associated active regions and may extend above the isolation region 102i, as required by the overall circuit layout. Furthermore, in sophisticated semiconductor devices, frequently, a plurality of dummy gates may be required, for instance with respect to enhancing overall process conditions when patterning the gate electrode structures 160a, 160b, 160c, 160d, while, in other cases, restrictive layout requirements may necessitate the provision of gate electrode lines to be placed in close proximity to one or more active regions, for instance as shown in the case of a gate electrode structure 160i, which extends along the active regions 102a, 102b. 
The active regions 102a, 102b, 102c, 102d are typically formed on the basis of well-established process strategies including the formation of appropriate trenches in a semiconductor layer so as to finally form the isolation region 102i, which thus laterally delineates the various active regions 102a, 102b, 102c, 102d. In sophisticated semiconductor devices, it may frequently be observed that, in transition areas between an active region and an isolation region, a pronounced surface topography, i.e., a recessing of the isolation region, is created, which may have a significant influence on the further processing of the device, for instance when forming gate electrode structures, incorporating a strain-inducing semiconductor material into portions of the active regions and the like. For example, in particular, end portions 160e of the gate electrode structures 160a, 160b, 160c, 160d may thus be formed at or in close proximity to any such recessed areas in the isolation regions 102i. Consequently, such areas, indicated by 120e, may be prone to significant gate failures, for instance with respect to insufficient encapsulation of sensitive materials and the like. Similarly, an edge area 1201 may also be identified as a critical region since also in this area a pronounced recessing or surface topography of the isolation region 102i is observed, thereby also affecting, for instance, the gate electrode structure 160i. Moreover, for the common gate electrode structures 160a, 160b, an intermediate region 120i, i.e., the portion of the gate electrode structures 160a, 160b in which the gate electrode structures “change” from a P-type electrode structure to an N-type electrode structure, may also represent a critical area with respect to gate failures.
FIG. 1b schematically illustrates a cross-sectional view of the device 100 according to the section indicated as Ib in FIG. 1a. As shown, a semiconductor layer 102, such as a silicon material and the like, is formed above a substrate 101 and comprises a plurality of active regions, for example the active region 102a, that is laterally delineated by the isolation region 102i. As discussed above, a pronounced recessing, indicated as 102r, is typically observed in the vicinity of the active region 102a. Consequently, the gate electrode structure 160i, which may require a reduced lateral offset from the active region 102a, may be formed at least partially within the recess 102r, thereby increasing the probability of causing gate failures and/or process non-uniformities during the further processing. The gate electrode structures 160a, 160i may have basically the same configuration and may comprise a gate dielectric material 161, which may include a high-k dielectric material such as hafnium oxide and the like, followed by a metal-containing electrode material 162, which also typically includes a work function metal species, such as aluminum and the like. Furthermore, typically, a semiconductor-based electrode material 163, such as silicon, is formed above the electrode material 162, followed by a dielectric cap layer or layer system 165, which is typically comprised of silicon nitride and the like. Furthermore, frequently, the electronic characteristics of at least some active regions have to be adjusted on the basis of an additional dedicated semiconductor material, as indicated by 103, which may be provided in the form of a semiconductor alloy, such as a silicon/germanium alloy, having a specified material composition and thickness. For example, a silicon/germanium material is frequently used in active regions of P-channel transistors in order to adjust a required band gap offset with respect to N-channel transistors in combination with complex high-k metal gate electrode structures. Consequently, providing the semiconductor alloy 103 as a part of the active region 102a in a selective manner may additionally contribute to a more pronounced topography between the active region 102a and the isolation region 102i. Furthermore, as discussed above, the material 161 and in particular the material 162 have to be encapsulated so as to avoid undue shift of material characteristics and thus characteristics of the resulting transistors, which is typically accomplished by providing a liner or spacer 164, for instance comprised of silicon nitride. Moreover, as explained before, a width of the spacer 164 may not be arbitrarily increased since increased spacer width may significantly influence the further processing and in particular the finally obtained transistor characteristics, for example in view of lateral dopant profiles of drain and source regions, the lateral offset of the strain-inducing semiconductor material that may be incorporated into at least some of the active regions and the like. Due to the pronounced recessing of the isolation region 102i in the vicinity of the active region 102a, however, a reduced degree of encapsulation or even dopant areas of the materials 161, 162 may occur, thereby giving rise to significant gate failures and/or process non-uniformities.
FIG. 1c schematically illustrates the device 100 according to a cross-sectional view as indicated by Ic in FIG. 1a. As shown, the gate electrode structure 160b may extend with its end portion 160e into the recess 102r, thereby also giving rise to an insufficient encapsulation of the materials 161 and 162 by the liner or spacer 164, as shown in FIG. 1c. 
Consequently, due to the recessed configuration of the isolation region 102i, a certain probability of “footing” of the gate electrode structures may be induced during the process sequence for patterning the gate electrode structures, which may result in a thinned liner material covering the sidewall portions of the materials 161 and 162, or one or both of these materials may even be exposed by the spacer 164, as is, for instance, shown in FIGS. 1b and 1c. 
The semiconductor device 100 as shown in FIGS. 1b and 1c is typically formed on the basis of the following process strategy. The isolation region 102i is formed in the semiconductor layer 102 on the basis of sophisticated lithography, etch, deposition, anneal, planarization and removal techniques in order to form trenches in the layer 102 and subsequently fill the trenches with an appropriate dielectric material, such as silicon dioxide and the like. Thereafter, the electronic characteristics of the active regions are adjusted, for instance, by implanting appropriate well dopant species using well-established masking regimes. Next, the process sequence is typically applied in order to selectively provide the material 103, for instance within the active regions of P-channel transistors, which typically includes the formation of a hard mask material, such as a silicon dioxide material, which is selectively removed from the active regions of P-channel transistors, such as the active region 102a. Thereafter, a selective epitaxial growth process is applied in which the deposition of the desired semiconductor alloy is restricted to exposed silicon surface areas, while a pronounced material deposition on dielectric surface areas is suppressed. Thereafter, the growth mask is removed from the active regions and the further processing is continued by forming the gate electrode structures. It is to be noted, however, that the process sequence for forming the hard mask material, the selective deposition, which may include additional cleaning processes and the like, may significantly contribute to the generation of the recesses 102r, in particular in the vicinity of the active regions of P-channel transistors. The patterning of the gate electrode structures is typically accomplished by forming the gate dielectric material 161 and appropriate electrode materials in the form of the layer 162, which, however, is typically provided with different characteristics for P-channel transistors and N-channel transistors, or generally for different types of transistors, thereby also requiring a plurality of deposition and patterning processes. Thereafter, the silicon material 163 in combination with the cap layer 165 is deposited and patterned on the basis of any appropriate patterning strategy, for instance applying a double exposure/double etch strategy for patterning the material 165, which may then be efficiently used as a hard mask for etching through the materials 163, 162 and 161 on the basis of well-established etch recipes. Next, the spacer 164 is formed by depositing, for instance, a silicon nitride layer using well-established deposition techniques and patterning the layer into the spacer elements 164, which, however, may be performed at different process stages for different types of transistors, for instance when selectively incorporating a strain-inducing semiconductor material into some of the active regions.
FIG. 1d schematically illustrates a cross-sectional view of the device 100 according to the section Id in FIG. 1a, wherein the gate electrode structure 160a thus represents a common gate electrode structure connecting the active region 102a of a P-channel transistor with the active region 102b of an N-channel transistor. In the manufacturing stage shown, the gate electrode structure 160a is already patterned in accordance with device requirements and a spacer layer 164s is provided so as to encapsulate the sensitive materials 161, 162, as discussed above. In some sophisticated approaches, as already explained before, the spacer layer 164s may be patterned differently above the active regions 102a, 102b, for example when a strain-inducing material is to be incorporated into the active region 102a. In this case, a dedicated etch mask 121b is used for covering the active region 102b and a corresponding portion of the gate electrode structure 160a while exposing the device 100 to a reactive etch atmosphere. Thereafter, the processing may be continued, for instance, by etching into the active region 102a and forming therein a strain inducing-semiconductor material and the like. In a further advanced manufacturing stage, the spacer layer 164s may also be patterned into spacer elements above the active region 102b, thereby requiring a further mask 121a in order to protect the previously formed spacer elements formed adjacent to and above the active region 102a. If, however, a certain degree of misalignment, as indicated by 121o, is induced, a portion of the spacer layer 164s may be exposed twice to the corresponding reactive etch atmosphere, thereby significantly reducing the spacer thickness above the isolation region 102i between the active regions 102b, 102a. Consequently, during the further processing, this insufficient encapsulation may result in significant material removal, in particular of the layer 162, for instance caused by highly efficient cleaning recipes using SPM/APM, which may result in gate failures and the like. Furthermore, generally, the removal of a portion of the layer 162 in areas of gate electrode structures that are formed above the isolation regions 102i may result in reduced mechanical stability, which in turn may cause material delamination and the like during the further processing.
Moreover, as is evident from FIG. 1d, the recessing of the isolation region 102i, at least in the vicinity of the active regions 102b, 102a, effectively results in a “three-dimensional”channel, in particular in the active region 102a, due to the provision of the additional semiconductor material 103 since, in addition to the surface of the active regions, also a portion of the sidewalls thereof, indicated as 102s, is in contact with the gate electrode structure 160a. Consequently, the effective channel width, i.e., in FIG. 1d the horizontal extension, is increased by these sidewall surface areas 102s, which may, in particular in short width transistors, significantly contribute to the overall transistor characteristics. For example, in sophisticated static RAM areas, P-channel transistors have a design width of approximately 80 nm so that the height of the sidewall surface areas 102s of approximately 7 nm results in an effective width of 80+7+7 nm increases the effective width by approximately 20 percent. For the active region 102b, this effect is also present, however to a lesser degree.
Consequently, the above-described complex conventional process strategy may result in gate failures, process non-uniformities and variations of the resulting transistor characteristics, thereby making this per se promising approach less attractive.
In view of the situation described above, the present disclosure provides manufacturing techniques and semiconductor devices in which high-k metal gate electrode structures, or at least the critical materials thereof, may be provided in an early manufacturing stage, while avoiding or at least reducing the effects of one or more of the problems identified above.